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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Programmed input–output</span></span>
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<p><b>Programmed input–output</b> (also <b>programmable input/output</b>, <b>programmed input/output</b>, <b>programmed I/O</b>, <b>PIO</b>) is a method of <a href="Data_transmission" class="mw-redirect" title="Data transmission">data transmission</a>, via <a href="Input/output" title="Input/output">input/output</a> (I/O), between a <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU) and a <a href="Peripheral" title="Peripheral">peripheral</a> device,<sup id="cite_ref-CompArchOrg_1-0" class="reference"><a href="#cite_note-CompArchOrg-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> such as a <a href="Parallel_ATA" title="Parallel ATA">Parallel ATA</a> storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, in <a href="Direct_memory_access" title="Direct memory access">direct memory access</a> (DMA) operations, the CPU is uninvolved in the data transfer.
</p><p>The term can refer to either <a href="Memory-mapped_I/O" class="mw-redirect" title="Memory-mapped I/O">memory-mapped I/O</a> (MMIO) or port-mapped I/O (PMIO). PMIO refers to transfers using a special <a href="Address_space" title="Address space">address space</a> outside of normal memory, usually accessed with dedicated instructions, such as <samp>IN</samp> and <samp>OUT</samp> in <a href="X86" title="X86">x86</a> architectures. MMIO<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> refers to transfers to I/O devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices.
</p><p>The best known example of a PC device that uses programmed I/O is the Parallel AT Attachment (PATA) interface; however, the AT Attachment interface can also be operated in any of several DMA modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, keyboard and mouse <a href="PS/2_port" title="PS/2 port">PS/2 ports</a>, legacy <a href="MIDI" title="MIDI">MIDI</a> and <a href="Joystick" title="Joystick">joystick</a> ports, the interval timer, and older network interfaces.
</p>
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<div class="mw-heading mw-heading2"><h2 id="PIO_mode_in_the_ATA_interface">PIO mode in the ATA interface</h2></div>
<p>The PIO interface is grouped into different modes that correspond to different <a href="Transfer_rate" class="mw-redirect" title="Transfer rate">transfer rates</a>. The <a href="Electrical_signal" class="mw-redirect" title="Electrical signal">electrical signaling</a> among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.
</p><p>The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually Ultra Direct Memory Access (<a href="UDMA" title="UDMA">UDMA</a>)) interface was created to increase performance. The simple digital logic needed to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are unneeded as in <a href="Embedded_system" title="Embedded system">embedded systems</a>, or with <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate array</a> (FPGA) chips, where PIO mode can be used with no significant performance loss.
</p><p>Two additional advanced timing modes have been defined in the <a href="CompactFlash" title="CompactFlash">CompactFlash</a> specification 2.0. Those are PIO modes 5 and 6. They are specific to CompactFlash.
</p>
<table class="wikitable" style="text-align:center">
<caption>PIO modes
</caption>
<tbody><tr>
<th>Mode</th>
<th>Maximum transfer rate (MB/s)</th>
<th>Minimum cycle time</th>
<th>Standard where spec is defined
</th></tr>
<tr>
<td>Mode 0
</td>
<td>3.3
</td>
<td>600 <a href="1_E-9_s" class="mw-redirect" title="1 E-9 s">ns</a>
</td>
<td><a href="AT_Attachment" class="mw-redirect" title="AT Attachment">ATA-1</a>
</td></tr>
<tr>
<td>Mode 1
</td>
<td>5.2
</td>
<td>383 <a href="1_E-9_s" class="mw-redirect" title="1 E-9 s">ns</a>
</td>
<td>ATA-1
</td></tr>
<tr>
<td>Mode 2
</td>
<td>8.3
</td>
<td>240 <a href="1_E-9_s" class="mw-redirect" title="1 E-9 s">ns</a>
</td>
<td>ATA-1
</td></tr>
<tr>
<td>Mode 3
</td>
<td>11.1
</td>
<td>180 <a href="1_E-9_s" class="mw-redirect" title="1 E-9 s">ns</a>
</td>
<td>ATA-2
</td></tr>
<tr>
<td>Mode 4
</td>
<td>16.7
</td>
<td>120 <a href="1_E-9_s" class="mw-redirect" title="1 E-9 s">ns</a>
</td>
<td>ATA-2
</td></tr>
<tr>
<td>Mode 5
</td>
<td>20
</td>
<td>100 <a href="1_E-9_s" class="mw-redirect" title="1 E-9 s">ns</a>
</td>
<td><a href="CompactFlash" title="CompactFlash">CompactFlash</a> 2.0
</td></tr>
<tr>
<td>Mode 6
</td>
<td>25
</td>
<td>80 <a href="1_E-9_s" class="mw-redirect" title="1 E-9 s">ns</a>
</td>
<td>CompactFlash 2.0
</td></tr></tbody></table>
<div class="mw-heading mw-heading3"><h3 id="PIO_Mode_5">PIO Mode 5</h3></div>
<p>A PIO Mode 5 was proposed<sup id="cite_ref-ATA_Timing_Extension_For_ATA-3_3-0" class="reference"><a href="#cite_note-ATA_Timing_Extension_For_ATA-3-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> with operation at 22 MB/s, but was never implemented on hard disks because CPUs of the time would have been crippled waiting for the hard disk at the proposed PIO 5 timings, and the <a href="Direct_memory_access" title="Direct memory access">DMA</a> standard ultimately obviated it. While no <a href="Hard_disk_drive" title="Hard disk drive">hard disk drive</a> was ever manufactured to support this mode, some <a href="Motherboard" title="Motherboard">motherboard</a> manufacturers preemptively provided <a href="BIOS" title="BIOS">BIOS</a> support for it. PIO Mode 5 can be used with CompactFlash cards connected to ATA via CF-to-ATA adapters.
</p>
<div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2></div>
<ul><li><a href="WDMA_(computer)" title="WDMA (computer)">WDMA (computer)</a> – single/multi-word DMA</li>
<li><a href="AT_Attachment" class="mw-redirect" title="AT Attachment">AT Attachment</a> – ATA specification</li>
<li><a href="Input/output" title="Input/output">Input/output</a></li>
<li><a href="Interrupt" title="Interrupt">Interrupt</a></li>
<li><a href="List_of_device_bandwidths" class="mw-redirect" title="List of device bandwidths">List of device bandwidths</a></li>
<li><a href="CompactFlash" title="CompactFlash">CompactFlash</a></li></ul>
<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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<li id="cite_note-CompArchOrg-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-CompArchOrg_1-0">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">
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</style><cite id="CITEREFHayes1978" class="citation book cs1">Hayes, John P. (1978). <i>Computer Architecture and Organization</i>. McGraw-Hill International Book Company. p. 419. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-07-027363-4</bdi>.</cite></span>
</li>
<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite id="CITEREFStallings2012" class="citation book cs1">Stallings, William (2012). <i>Computer Organization and Architecture</i> (9th ed.). Pearson.</cite></span>
</li>
<li id="cite_note-ATA_Timing_Extension_For_ATA-3-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-ATA_Timing_Extension_For_ATA-3_3-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFChen1995" class="citation web cs1">Chen, Joseph (January 10, 1995). <a rel="nofollow" class="external text" href="https://www.t10.org/ftp/t10/document.95/95-122r0.pdf">"Proposed 22 MByte/Sec ATA Timing Extension for ATA-3"</a> <span class="cs1-format">(PDF)</span>. <i>T10.org</i>. Technical Committee T10 (X3T10). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100620052300/https://www.t10.org/ftp/t10/document.95/95-122r0.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on June 20, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">February 19,</span> 2020</span>.</cite></span>
</li>
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